Performance analysis of short channel effects immune <scp>JLFET</scp> with enhanced drive current
Abhishek Raj, Kunal Singh, Shashi Kant Sharma
Abstract
Abstract This manuscript reports analog/RF and noise analysis of a novel junctionless field effect transistor. To reduce the gate induced drain leakage (GIDL), step‐gate‐oxide structure is used with a high‐k buried oxide (BOX) which subsequently reduces I OFF . The off current and gate capacitance is reduced by including step‐gate‐oxide in high k‐BOX JLFET due to increase in the band to band tunneling (BTBT) width. The DIBL is reduced significantly to 0.014 which is 60% less as compared to high‐k BOX JLFET (HB JLFET). For different length and thickness of the step‐gate‐oxide, the analog/RF and noise performance of the step‐gate‐oxide JLFET with high‐k BOX (SGO HB JLFET) have also been investigated in detail. Silvaco TCAD simulation of the proposed structure for 20 nm channel length shows an extremely high I ON / I OFF ratio of ~10 8 . The subthreshold swing for the simulated structure was also found to be considerably low (82 mV/dec).