Dirac-source diode with sub-unity ideality factor
Gyuho Myeong, Wongil Shin, Kyunghwan Sung, Seung‐Ho Kim, Hongsik Lim, Boram Kim, Taehyeok Jin, Ji Hoon Park, Taehun Lee, Michael S. Fuhrer, Kenji Watanabe, Takashi Taniguchi, Fei Liu, Sungjae Cho
Abstract
Abstract An increase in power consumption necessitates a low-power circuit technology to extend Moore’s law. Low-power transistors, such as tunnel field-effect transistors (TFETs), negative-capacitance field-effect transistors (NC-FETs), and Dirac-source field-effect transistors (DS-FETs), have been realised to break the thermionic limit of the subthreshold swing (SS). However, a low-power rectifier, able to overcome the thermionic limit of an ideality factor (η) of 1 at room temperature, has not been proposed yet. In this study, we have realised a DS diode based on graphene/MoS 2 /graphite van der Waals heterostructures, which exhibits a steep-slope characteristic curve, by exploiting the linear density of states (DOSs) of graphene. For the developed DS diode, we obtained η < 1 for more than four decades of drain current (η ave_4dec < 1) with a minimum value of 0.8, and a rectifying ratio exceeding 10 8 . The realisation of a DS diode represents an additional step towards the development of low-power electronic circuits.