Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine
A.K. Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao
Abstract
This paper presents a split CPU-FPGA Multi-Scalar Multiplication (MSM) engine written in Hardcaml. Hardcaml MSM was submitted to the 2022 ZPrize cryptography competition and won 1st place in the FPGA track. Hardcaml MSM targets the BLS12-377 elliptic curve and is currently the lowest-latency implementation utilizing FPGAs published. For a MSM of order 2^26 we achieve a single-round MSM latency of 5.518s and average power of 52W, with our design running at 278MHz. When performing multiple rounds of MSM with the same base points but random scalars, we are able to further mask host I/O and memory latency and reduce latency to 5.083s. This is a latency improvement of 13% over the previously fastest reported FPGA solution, and an improvement of 472% when compared to state of the art open-source CPU library gnark-crypto.