Modern Trends in Microelectronics Packaging Reliability Testing
Emmanuel Bender, J.B. Bernstein, Duane S. Boning
Abstract
In this review, recent trends in microelectronics packaging reliability are summarized. We review the technology from early packaging concepts, including wire bond and BGA, to advanced techniques used in HI schemes such as 3D stacking, interposers, fan-out packaging, and more recently developed silicon interconnect fabric integration. This review includes approaches for both design modification studies and packaged device validation. Methods are explored for compatibility in new complex packaging assemblies. Suggestions are proposed for optimizations of the testing practices to account for the challenges anticipated in upcoming HI packaging schemes.
Topics & Concepts
Ball grid arrayMicroelectronicsInterposerCompatibility (geochemistry)Reliability (semiconductor)InterconnectionWire bondingElectronic packagingReliability engineeringPackaging engineeringIntegrated circuit packagingEngineeringComputer scienceSystems engineeringManufacturing engineeringIntegrated circuitSolderingMechanical engineeringMaterials scienceElectronic engineeringNanotechnologyElectrical engineeringTelecommunicationsComposite materialPhysicsChemical engineeringQuantum mechanicsChipPower (physics)Etching (microfabrication)Layer (electronics)Electronic Packaging and Soldering Technologies3D IC and TSV technologiesCopper Interconnects and Reliability