Analysis of BTI, SHE Induced BTI and HCD Under Full V<sub>G</sub>/V<sub>D</sub> Space in GAA Nano-Sheet N and P FETs
Nilotpal Choudhury, Uma Sharma, Huimei Zhou, Richard G. Southwick, Miaomiao Wang, Souvik Mahapatra
Abstract
An ultrafast (10ps delay) characterization method is used to measure threshold voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) owing to Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) stress in N and P channel Gate All Around (GAA) NSFETs. ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> time kinetics at various gate bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and temperature (T) for BTI and at various VG and drain bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) for HCD is analyzed. Contribution from Self Heat Effect (SHE) induced BTI to overall HCD is estimated under full V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> /V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> space and pure HCD contribution is determined.