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MLIR: Machine Learning based IR Drop Prediction on ECO Revised Design for Faster Convergence

Santanu Kundu, Manoranjan Prasad, Sashank Nishad, Sandeep Nachireddy, K Harikrishnan

202212 citationsDOI

Abstract

The on-chip power delivery network (PDN) is an essential element of physical implementation that strongly determines functionality, quality, and reliability of an IC. During signoff phase, several engineering-change-order (ECO) iterations are needed to ensure that each instance of the design should meet IR drop specification. Even though the design remains very similar after ECO changes, conventional PDN analysis in industry standard CAD tool takes several hours of simulation runtime to determine IR drop. Our goal is to reduce this runtime in each iteration to evaluate the ECO changes and fix the violating cells immediately, prior to run conventional PDN signoff tool. Hence, improving the number of iteration and achieving faster PDN Machine Learning methodology for fast IR drop prediction where we have used regression techniques to predict static IR drop values and classification techniques to predict dynamic IR drop violating cells. We have evaluated the importance of every feature that contributes to the IR drop. We have also interpreted the predicted output using Explainable AI method. While inferencing on a ~1M instance industry design, we have achieved 0.997 R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -Score, −5.21 mV maximum absolute error, and $117\mu\mathrm{V}$ RMSE in static IR Drop prediction. On dynamic IR drop prediction, we have achieved 0.999 accuracy, 0.909 $F1\_{}{Score}$, 0.893 Precision, and 0.926 Recall.

Topics & Concepts

Power network designDrop (telecommunication)Computer scienceConvergence (economics)Mean squared errorFeature engineeringMachine learningAlgorithmDrop outRegressionArtificial intelligenceDeep learningChipMathematicsStatisticsEconomic growthEconomicsDemographic economicsTelecommunicationsVLSI and Analog Circuit TestingVLSI and FPGA Design TechniquesLow-power high-performance VLSI design
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