Virtual Intermediate Bus CPU Voltage Regulator
Yenan Chen, Ping Wang, Hsin Cheng, Gregory Szczeszynski, Stephen Allen, David M. Giuliano, Minjie Chen
Abstract
This article presents a merged two-stage 48-V-to-1-V point-of-load (PoL) architecture with a 24-V virtual intermediate bus (VIB) for CPU voltage regulator applications. The VIB-PoL architecture includes two power conversion stages linked by a 24-V VIB with a significant voltage ripple. The first stage is a 2:1 interleaved charge pump, which converts 48 to 24 V. The second stage comprises multiple interleaved four-level series-capacitor buck modules with coupled inductors, converting 24 V to regulated 1 V with an equivalent voltage conversion ratio of 6:1. The VIB-PoL architecture achieves high efficiency and high power density by reducing the power conversion stress of both stages and eliminating the intermediate bus capacitors. A 48-V-to-1-V 640-A CPU voltage regulator with a peak power stage efficiency of 95.2% (93.3%, including gate driver loss), a full-load efficiency of 84.4% (83.1%, including gate driver loss), and a power density of 463 W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^3$</tex-math></inline-formula> (at 1-V output with liquid cooling) is built and tested to demonstrate the VIB-PoL architecture.