Mitigating IR-Drop with Design Technology Co-Optimization for Sub-Nanometer Node Technology
Dohyeon Lee, Heecheol Hwang, Hyunteck Oh, Yongchan Ban
Abstract
In this paper, we have proposed various approaches for reducing IR (Voltage)-drop with the best trade-off between the PPA (performance, power, area) and the IR tolerance for sub-nanometer node designs and technologies. The proposed approaches include the optimization of power distribute network (PDN), clock-cell placement, and cell placement in logic paths.
Topics & Concepts
Power network designNanometreNode (physics)Drop (telecommunication)Logic gateComputer scienceNanoelectronicsElectronic engineeringVoltage dropLogic synthesisVoltageEmbedded systemElectrical engineeringEngineeringMaterials scienceNanotechnologyStructural engineeringChemical engineeringInterconnection Networks and SystemsSemiconductor materials and devicesLow-power high-performance VLSI design