Identification of two trapping mechanisms responsible of the threshold voltage variation in SiO2/4H-SiC MOSFETs
Patrick Fiorenza, Filippo Giannazzo, Salvatore Cascino, Mario Saggio, Fabrizio Roccaforte
Abstract
A method based on cyclic gate bias stress followed by a single point drain current measurement is used to probe the interface or near-interface traps in the SiO2/4H-SiC system over the whole 4H-SiC bandgap. The temperature-dependent instability of the threshold voltage in lateral MOSFETs is investigated, and two separated trapping mechanisms were found. The experimental results corroborate the hypothesis that one mechanism is nearly temperature independent and it is correlated with the presence of near-interface oxide traps that are trapped via tunneling from the semiconductor. The second mechanism, having an activation energy of 0.1 eV, has been correlated with the presence of intrinsic defects at the SiO2/4H-SiC interface.