A Load Adaptive Digital Gate Driver IC With Integrated 500 ksps ADC for Drive Pattern Selection and Functional Safety Targeting Dependable SiC Application
Shusuke Kawai, Takeshi Ueno, Hiroaki Ishihara, Satoshi Takaya, Koutaro Miyazaki, Kohei Onizuka, Hiroki Ishikuro
Abstract
A fully integrated load adaptive digital gate driver is proposed for high-speed and dependable SiC applications. It breaks the trade- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> between surge/ringing and switching loss over a wide load range of 3–15 A by selecting the gate patterns stored in 8 channel 1.5 kb look up table (LUT). The principle of voltage ringing during turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> of power devices is analyzed, and a method of temporarily controlling the gate current in the opposite direction is found to be effective. A proposed time resolution expansion technique allows the output of optimal waveforms based on theory without increasing the memory size, achieves the surge/ringing suppression of 51% and reduce the LUT size by 1/12. The integrated 500 ksps successive approximation register analog to digital converter (ADC) with steady sampling and automatic power supply voltage (VDD) selection schemes senses not only the load current, but also the surge and the short circuit for functional safety.