A PVT-Tolerant Oscillation-Collapse-Based True Random Number Generator With an Odd Number of Inverter Stages
Jaehan Park, Byungjun Kim, Jae‐Yoon Sim
Abstract
This brief proposes a PVT-tolerant true random number generator (TRNG) based on a ring oscillator (RO) with an odd number of inverter stages. By introducing a Muller C-element in each racing path of the RO, the TRNG successfully eliminated the need of collapse detection circuits. The proposed topology enables a bidirectional controllability in the number of cycles to collapse (CTC) and provides flexibility for the number of random bits per cycle. Implemented TRNG in 40nm CMOS shows intrinsic robustness against PVT variations across a supply range of 0.5V-to-1.4V and a temperature range of −40°C-to-125°C without calibration. It consumes 0.0107 nJ/bit at 0.9V and occupies 305.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {\mathrm{ m}}^{2}$ </tex-math></inline-formula> .