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3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling

ChingYao Huang, G. Dewey, Ehren Mannebach, A. Phan, P. Morrow, W. Rachmady, I‐Cheng Tung, N. Thomas, Urusa S. Alaan, R. Paul, Nafees Kabir, B. Krist, A. Oni, M. Mehta, M. Harper, P. Nguyen, Ryan Keech, Suresh Vishwanath, Kai Loon Cheong, Jaehyeon Kang, A. D. Lilak, M. Metz, Scott B. Clendenning, B. A. Turkot, Richard E. Schenker, Hui Jae Yoo, M. Radosavljević, J. Kavalieros

2020115 citationsDOI

Abstract

We demonstrate 3-D self-aligned stacked NMOS-on-PMOS multiple Si nanoribbon transistors with successful integration of vertically stacked dual source/drain EPI process and vertically stacked dual metal gate process. Both top NMOS and bottom PMOS show high on-state performance and superior short channel control. A functional CMOS inverter is also demonstrated with well-balanced voltage transfer characteristics. The 3-D self-aligned stacked CMOS nanoribbon transistor is demonstrated as a promising transistor architecture to continue Moore’s law scaling.

Topics & Concepts

PMOS logicNMOS logicTransistorMaterials scienceInverterCMOSOptoelectronicsMOSFETLogic gateElectrical engineeringVoltageEngineeringSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignNanowire Synthesis and Applications
3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling | Litcius