17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input
Hongzhi Zhao, Minglei Zhang, Yan Zhu, Chi‐Hang Chan, Rui P. Martins
Abstract
By increasing the number of bits in each conversion cycle, the sampling rate of SAR ADCs can be considerably extended while maintaining superior energy efficiency. Nevertheless, the hardware cost expands substantially, which in turn limits the speed/bit-per-cycle of multi-bit SAR ADCs. Compared with its single bit/cycle counterpart, the multi-bit SAR ADC additionally needs to generate multiple references and conduct multi-bit comparisons, posing power, timing, and area overheads. Figure 17.1.1 depicts three prior art techniques for producing the multi-reference with different mechanisms. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{In}$</tex> [1] with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2\mathrm{b}/\text{cycle}$</tex> design, the reference is provided by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2^{\mathrm{M}-1}-1$</tex> capacitive reference DACs <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{CDAC}_{\mathrm{R}})$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\phi_{\text{REF1}:\mathrm{N}\mathrm{E}\mathrm{F}\mathrm{l}\mathrm{N}}$</tex> where <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{M}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{N}$</tex> denote the number of bit conversions per cycle and the number of cycles, respectively. The 1-then-2b/cycle SAR ADC in [2] utilizes <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2^{\mathrm{M}-1}$</tex> capacitive DACs <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{CDAC}_{\mathrm{S}})$</tex> to generate the multi-reference. To save the pre-charge time, a fixed 1b conversion must be conducted in the first cycle. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{Although}$</tex> these designs secure a fast reference generation, either <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{CDAC}_{\mathrm{R}}$</tex> or <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{CDAC}_{\mathrm{S}}$</tex> scales exponentially with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{M}$</tex> , preventing high-speed operation with a large <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{M}$</tex> due to the substantial hardware cost and global reference/input load. The <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\mathrm{b}/\text{cycle}$</tex> design in [3] only requires two <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{CDAC}_{\mathrm{s}}$</tex> , with the multi-reference realized by level-shifting of the residue voltage with an interpolator. However, the resistive interpolator is supported by two static <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{open}-\text{loop}$</tex> amplifiers whose linearity and settling accuracy are critical, eventually occupying a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{long}$</tex> time before comparison. This work describes <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{a} \ 5\mathrm{b}/\text{cycle}$</tex> SAR ADC with one signal DAC facilitated by a time-domain quantizer (TD QTZ). The proposed linearized dynamic integrator-based voltage-to-time <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}2\mathrm{T})$</tex> buffer enables <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{a high}$</tex> -speed multi-bit/cycle operation, which simultaneously provides isolation between the TD QTZ and sampling front end, thus not only removing kickback noise from the QTZ but rendering a high input bandwidth (BW). With <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2\times -\text{time}$</tex> interleaving, the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$28\text{nm}$</tex> prototype aggregates a sampling rate of 2.8GS/s and consumes <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$18\text{mW}$</tex> under <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{a}\ 0.9\mathrm{V}$</tex> supply. The SNDR and SFDR at Nyquist input are 51. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$79\text{dB}$</tex> and 72. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$36\text{dB}$</tex> , respectively, leading to a 20. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3\text{fJ}/\text{conv}$</tex> . -step Walden <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{FoM}$</tex> .