A Compact I/Q Upconversion Chain for a 5G Wireless Transmitter in 65-nm CMOS Technology
Hyohyun Nam, Woo‐Jae Lee, Juho Son, Jung‐Dong Park
Abstract
A compact in-phase/quadrature (I/Q) upconversion chain with high linearity is presented for an integrated transceiver for 5G mobile communications. The upconverter includes 10-11.5-GHz upconversion chains, a quadrature signal generator (QSG) consisting of the two coupled current-mode logic latches, and inverting amplifiers to provide the rail-to-rail local oscillator (LO) swing with a 25% duty cycle for I/Q mixers which achieved 46.9 dB of image rejection ratio. A cross-coupled pair operating at weak inversion was used at the output of the upconverter and it improved the output of the third-order intercept point (OIP3) by 2.58 dB. The upconverter achieved a transmitter gain of 9.12 dB and an OIP3 of 14.45 dBm. The implemented I/Q upconverter with the QSG consumes 48.7 mW under a 1-V supply, and it occupies only 0.57 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of chip area including pads.