Randomized Testing of RISC-V CPUs Using Direct Instruction Injection
Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, Simon W. Moore
Abstract
This article presents a randomized testing framework for RISC-V implementations by using a technique called direct instruction injection for test injection. —Fei Su, Intel, USA
Topics & Concepts
Computer scienceOperating systemReduced instruction set computingEmbedded systemParallel computingInstruction setVLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisSoftware Testing and Debugging Techniques