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Trap Generation in Whole Gate Stacks of FeFET With TiN/Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub>/SiO<sub>x</sub>/Si (MFIS) Gate Structure During Endurance Fatigue

Jiahui Duan, Shujing Zhao, Fengbin Tian, Jinjuan Xiang, Kai Han, Tingting Li, Hao Xu, Xiaolei Wang, Wenwu Wang, Tianchun Ye

2022IEEE Transactions on Electron Devices21 citationsDOI

Abstract

This work investigates trap generation in gate stacks of ferroelectric field-effect transistor (FeFET) with TiN/Hf0.5Zr0.5O2/SiOx/Si gate structure during endurance fatigue by using the low-frequency noise method. We find that the traps are generated not only at Hf0.5Zr0.5O2/SiOx interface but also in both the Hf0.5Zr0.5O2 and SiOx. Our work provides evidence of defect generation inside the ferroelectric layer of FeFET during cycling. Furthermore, the traps in the SiOx are more detrimental to endurance fatigue. And the trap generation in the SiOx is more important than its initial trap density for endurance fatigue. Our work is helpful in deeply understanding the endurance of FeFET.

Topics & Concepts

TinMaterials scienceFerroelectricityOptoelectronicsTrap (plumbing)Field-effect transistorTransistorElectrical engineeringElectronic engineeringDielectricMetallurgyEngineeringVoltageEnvironmental engineeringFerroelectric and Negative Capacitance DevicesSemiconductor materials and devicesMXene and MAX Phase Materials
Trap Generation in Whole Gate Stacks of FeFET With TiN/Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub>/SiO<sub>x</sub>/Si (MFIS) Gate Structure During Endurance Fatigue | Litcius