11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology
Ramy Yousry, E-Hung Chen, Yu-Ming Ying, Mohammed Abdul-Latif, Mohammad Elbadry, Ahmed ElShater, Tsz-Bin Liu, Joonyeong Lee, Dhinessh Ramachandran, Kaiz Wang, Chih-Hao Weng, Mau-Lin Wu, Tamer Ali
Abstract
COVID-19 sparked a paradigm shift for businesses, education, and social life. The measures taken have emphasized, more than ever, the importance of on-line communication platforms. Online streaming services, education tools, and workplace communication tools all experienced a multifold increase in demand in 2020 as the world population was under a lockdown. Service providers' ability to meet these demands relies on the capacity of mega-scale data centers (MSDC). Hence, capacity and bandwidth of MSDCs are expected to grow exponentially. The transition from 12.8 to 51.2Tb/s switches for data centers leaf and spine is underway, and is expected to deploy starting in 2021~2022 [1]. Unfortunately, the increase of switch throughput comes with serious area, yield, and power limitations. To mitigate the problem, recent advances in chiplets and multi-die technologies for high throughput switches show a promising increase in yield and lower solution cost. Another direction is silicon photonic and ASIC co-integration, which allows for package throughput well beyond the electrical interface capability.