System-Level Test: State of the Art and Challenges
D. Appello, H. H. Chen, M. Sauer, Ilia Polian, Paolo Bernardi, M. Sonza Reorda
Abstract
System-level test (SLT) is gaining in importance in modern test flows. This paper summarizes recent industrial findings from three companies and discusses some of the still open questions. The first two reports focus on the optimization potentials due to defect coverage overlaps between SLT and other test insertions. Results observed on approximately 20 million manufactured 28nm and 40nm automotive system-on-chip (SoC) designs are reported. Costs and benefits of SLT are discussed and the potentials of a test results analytics platform are identified. The third report explores the role of marginalities among SLT fails. The post-silicon investigation of a CPU block in a 7nm 5G mobile SoC product aims at achieving a better understanding, whose fails are due to random variations versus systematic factors.