A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1^st/2^nd-Order DTC INL Calibration

Abstract

Modern system-on-chips (SoCs) integrate several independent on-chip clock generators to satisfy diverse specifications for different modules, such as microprocessors, memories, I/O interfaces, and power management. Conventionally, multiple PLLs are used in SoCs to provide various frequency outputs; however, this method incurs a considerable silicon area, power, cost, and the overall system complexity. Fractional output dividers (FODs), which are composed of a multi-modulus divider (MMD), a digital-to-time converter (DTC), and a digital controller, have been proved to be an effective method for multiple independent clock generation. However, the DTC characteristic is PVT sensitive, and any gain mismatch/integral nonlinearity (INL) generates large spurs, which degrade spectral purity and clock jitter. The traditional DTC-gain-calibration algorithm, which is widely applied in PLLs, requires a feedback path to reflect DTC-gain mismatch, which prohibits its use in FODs with the open-loop structure. As shown in the upper left of Fig. 14.2.1, an extra complementary-replica DTC <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{DTC}_{\mathrm{c}})$</tex> is adopted to calibrate DTC gain (Kdtc) [1]. However, the replica DTCs consume large power and area while leading to replica-DTC mismatch concerns, which can seriously degrade the calibration effectiveness. Although the extra replica DTC can be removed by capturing the delay of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{DTC}_{\mathrm{M}}$</tex> when the digital control word for DTC (Ddcw) equals to 0 and full code alternatively [2]; unfortunately, this method only makes an effective comparison when delta-sigma modulator (DSM) produces an overflow, resulting in a long calibration-convergence time for some frequency-control words (FCWs). Furthermore, neither of the above solutions takes DTC INL into account; thus, the effectiveness of the spur reduction is limited. Extracting a periodic pattern with digital filters and subtracting it from the input FCW is another approach to reduce FOD spurs [3]. Nevertheless, the calibration effectiveness heavily depends on prior knowledge of spur frequencies and needs complex and onerous preliminary measurements. In order to overcome the above-mentioned issues, this paper presents an FOD with an auxiliary-PLL (aux-PLL)-based background <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0^{\text{th}}/1^{\text{st}}/2^{\text{nd}}$</tex> -order DTC-INL-calibration scheme. The aux-PLL functions as a frequency domain filter, which naturally tracks carrier frequency of the input clock. Thus, prior knowledge and foreground calibration are not needed. Compared to the reported -55dBc spur level in [1] and -65dBc spur level in [2], the proposed FOD achieves less than -80dBc worst-case spurious tones, thanks to the proposed aux-PLL -based <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0^{\text{th}}/1^{\text{st}}/2^{\text{nd}}$</tex> -order DTC-INL-calibration algorithm.

Topics & Concepts