Monolithic 3D Integration of Vertically Stacked CMOS Devices and Circuits with High-Mobility Atomic-Layer-Deposited In <sub>2</sub> O <sub>3</sub> n-FET and Polycrystalline Si p-FET: Achieving Large Noise Margin and High Voltage Gain of 134 V/V
Wenjing Tang, Zhaobo Wang, Zehao Lin, Lei Feng, Zhicong LIU, Xiangyou Li, P. D. Ye, Xiao Guo, Mengwei Si
Abstract
In this work, we demonstrate the monolithic 3D integration (M3D) of vertically stacked p-type low-temperature polycrystalline silicon (LTPS) top-gate transistor and n-type back gate oxide semiconductor transistor, similar to a complementary field-effect transistor (CFET) structure, for complementary metal-oxide-semiconductor (CMOS) logic applications, with a low thermal budget of 450°C. High-performance logic devices and circuits (inverter, NAND, NOR) are demonstrated with a high voltage gain of 134.3 V/V and a large noise margin of 0.84 V at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> of 2 V, which are among the best values in reported CMOS inverters by oxide semiconductor n-FET and LTPS p-FET. These devices are enabled by a high electron mobility atomic-layer deposited (ALD) In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> as n-channel to balance the high hole mobility of LTPS. The fabricated ALD In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> n - FETs exhibit high electron mobility $\gt 100$ cm $^{2} / V\cdot s$ on $\text{SiO}_{2}/\text{Si}$ substrate and mobility of 23.8 cm $^{2} /V\cdot s$ in the n-FET of the M3D CMOS inverter, which is the highest number in reported CMOS inverters with oxide semiconductor n-FETs and LTPS p-FETs.