Modeling Gate Leakage Current for p-GaN Gate HEMTs With Engineered Doping Profile
Mojtaba Alaei, Matteo Borga, Elena Fabris, Stefaan Decoutere, Johan Lauwaert, Benoit Bakeroot
Abstract
The forward bias gate leakage current and forward gate breakdown voltage are important properties of p-GaN gate high-electron-mobility transistors (HEMTs). An engineered doping profile in the p-GaN layer results in a higher gate breakdown voltage and a lower forward bias gate leakage current. The use of such a technique puts additional requirements on the compact models that are used for these p-GaN gate HEMTs. An accurate compact model is needed, which considers a change in the doping profile in the p-GaN layer of these devices. This article reviews the relationship between the gate bias and the voltage drops at the different junctions in the gate structure (i.e., at the metal/p-GaN Schottky junction and the p-GaN/AIGaN/GaN junctions) considering an engineered doping profile. This relationship is then used to model the drain-source current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {DS}}$ </tex-math></inline-formula> ) and gate leakage current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_G$ </tex-math></inline-formula> ). Three different regimes in the gate current have been considered in the model: Poole-Frenkel (PF) under low bias, thermionic emission (TE) in the medium bias range, and thermally assisted tunneling (TAT) at higher bias.