A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit
Chua‐Chin Wang, Ralph Gerard B. Sangalang, I‐Ting Tseng
Abstract
Memory arrays such as SRAM cells are responsible to the high-power consumption of modern digital systems. This investigation proposed an SRAM utilizing an ultra-low power cell, implemented using the 16-nm FinFET CMOS technology. Voltage supply selection of the static RAM cells is done by gating the wordline (WL) enable. In standby mode, the cell wordline is not activated, where the cell operates on a lower voltage level so that the stored bit status is still retained. On the other hand, the normal mode is activated when the wordline of the cell is enabled. Theoretical derivations, all-PVT-corner post-layout simulations, and measurement results were provided for verification of the functionality and performance. An SRAM of 1-kb capacity is designed based on the propose cell. The on-silicon measurement demonstrates 0.006832 fJ (energy/bit) at 500 MHz clock rate and 0.8 V supply.