An 8-to-12-Bit Resolution-Reconfigurable SAR ADC With Fast-Window-Switching Technique
Yuhua Liang, Shida Song, Zhangming Zhu
Abstract
This brief presents a resolution-reconfigurable successive-approximation-register (SAR) analog-to-digital converter (ADC). The reconfigurable capacitor digital-to-analog converter (CDAC) is designed to support 8/10/12-bit resolution modes. In order to mitigate the nonlinearity introduced by capacitor mismatch and suppress the transition glitch during the most significant bit trial in 10/12-bit modes, the Fast-Window-Switching (FWS) technique is proposed. The FWS technique can improve the linearity of the ADC without increasing the total capacitance of the CDAC, thus reducing the chip area and the burden of input buffers. The prototype is fabricated in a 180-nm CMOS process and occupies an active area of 0.23mm2. On the condition of a sampling rate of 10-MS/s, the achieved SNDR and SFDR are 48.3dB and 60.8dB in the 8-bit mode. With the FWS performing its role in the 10/12-bit mode, the ADC achieves 59.2dB/65.5dB SNDR and 73.4dB/79.6dB SFDR, and consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$350\mu $ </tex-math></inline-formula>W/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$580\mu $ </tex-math></inline-formula>W at 1.8V supply.