A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS
Hyungrok Do, Jung-Woo Sull, Seunghyun Lee, Kwang‐Ho Lee, Deog‐Kyoon Jeong
Abstract
The data-rate requirement for a data center interconnect is being switched to 400 Gb/s. For the optical interface, the electro-optical transmitter chip designed in the CMOS process has been proposed rather than the BiCMOS process as technology advances. On the other hand, vertical-cavity surface-emitting laser (VCSEL) has been a popular candidate for the optical modulation device of the 400 GbE interconnect because of its cost and packaging efficiency [1] –[7]. However, the high operating voltage, nonlinear effects, and low bandwidth are problems to be overcome by the VCSEL driver to transmit high-speed pulse-amplitude-modulation-4 (PAM-4). The pattern-detecting equalization is proposed [3], [6] to compensate for the nonlinearity, and the driver combines MSB-LSB with a 1-bit DAC scheme to produce PAM-4 output [3], [5–6]. However, pattern detection requires power-consuming additional blocks. The combining at the driver needs an additional pre-driver and increases driver drain capacitance which lowers the bandwidth. This paper presents a PAM-4 64 Gb/s VCSEL transmitter (TX) for 400 GbE with 3-tap sub-UI asymmetric feed-forward equalizer (FFE) fabricated in 40 nm CMOS technology. The quarter-rate system and the PAM-4 combining 8:1 multiplexer (MUX) are employed for clocking power reduction. The sub-UI FFE and combining-ahead scheme compensate for low bandwidth. The TX achieves a power efficiency of 2.09 pJ/bit at PAM-4 64 Gb/s.