29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification
Jong‐Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng‐Fan Chang, Arijit Raychowdhury
Abstract
As memory-centric workloads (AI, graph-analytics) continue to gain momentum, technology solutions that provide higher on-die memory capacity/bandwidth can provide scalability beyond SRAM. Resistive RAM (RRAM) owing to (1) higher bit-density (2-4× of SRAM), (2) CMOS process/voltage compatibility, (3) nano-second read (RD) and (4) non-volatility has emerged as a promising candidate [1]. In spite of early prototypes, several technology challenges remain, and need to be addressed through circuit-technology co-design [1]. This paper presents a 64Kb RRAM macro supporting: (1) a programmable (1 to 9) number of row-accesses (N) to enable vector-matrix multiplication (referred to as compute-in-memory, or CIM) for a target algorithm-level inference-accuracy [2] -[8], (2) voltage-based RD with active feedback, advancing the state-of-the-art current-based RD, targeted for the low ratio between the high-resistance-state (HRS) and low-resistance-state (LRS) in typical RRAM, (3) RD-disturb tolerance under RRAM drift, through embedded RD-disturb monitor and write (WR)-back and (4) in-situ WR verification to enable a tight resistance distribution.