Analysis of Nanosheet Field-Effect Transistor With Local Bottom Isolation
Jiwon You, Hyunwoo Kim, Daewoong Kwon
Abstract
We propose a three-channel-based nanosheet field-effect transistor (BO NSFET <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3-channel}}$</tex-math> </inline-formula> ) adopting a bottom isolation (BO) under inner gate regions to alleviate subleakage current as well as parasitic capacitance, simultaneously. To thoroughly evaluate the superiority of the proposed device, the conventional four-channel-based NSFETs were used with punchthrough stop (PTS) doping (NSFET <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{4-channel}}$</tex-math> </inline-formula> ) and BO scheme (BO NSFET <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{4-channel}}$</tex-math> </inline-formula> ) as references, and the electrical characteristics for each device were investigated using the 3-D technology computer-aided design (TCAD) simulations. For the proposed BO NSFET <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3-channel}}$</tex-math> </inline-formula> , although the PTS doping was not applied, it was observed that off-current and subthreshold swing (SS) characteristics are almost the same with the conventional NSFET <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{4-channel}}$</tex-math> </inline-formula> with PTS doping because BO scheme can physically suppress direct source-to-drain leakage. It can also have less gate-induced drain leakage (GIDL) between the inner gate and substrate by BO scheme and small drain-to-substrate junction leakages by PTS doping skip. Furthermore, it was revealed that parasitic gate oxide capacitances are decreased about 9.03% compared to the references by adding the BO scheme under the inner gates, which hinders the bottom channel formation. As a result, it was confirmed that the intrinsic delay of the proposed device is improved 7.1% at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}_{\text{D,\biosc{off}}}$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula> 2 nA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m compared to the conventional one. This proposed BO scheme would be beneficial for both n-and p-type NSFET devices and can provide valuable insights for the design of the next-generation logic devices.