Formation of high-quality SiO<sub>2</sub>/GaN interfaces with suppressed Ga-oxide interlayer via sputter deposition of SiO<sub>2</sub>
Kentaro Onishi, Takuma Kobayashi, Hidetoshi Mizobata, Mikito Nozaki, Akitaka Yoshigoe, Takayoshi Shimura, Heiji Watanabe
Abstract
Abstract While the formation of a GaO x interlayer is key to achieving SiO 2 /GaN interfaces with low defect density, positive fixed charge is rather easily generated through the reduction of GaO x layer if the annealing conditions are not properly designed. In this study, we minimized the unstable GaO x layer by sputter SiO 2 deposition. Negligible GaO x growth was confirmed by synchrotron radiation X-ray photoelectron spectroscopy, even when post-deposition oxygen annealing up to 600 °C was performed. A MOS device with negligible capacitance–voltage hysteresis, stable flat-band voltage, and low leakage current was demonstrated by performing oxygen and forming gas annealing at temperatures of 600 °C and 400 °C, respectively.