Performance analysis and reliability estimation of five‐level rectifier
Manish Kumar Barwar, Lalit Kumar Sahu, Pallavee Bhatnagar, Krishna Kumar Gupta, Allamsetty Hema Chander
Abstract
Abstract Multilevel rectifiers (MLRs) have been gaining popularity in a variety of applications due to their many advantages over two‐level rectifiers such as reduced voltage stress on power switches, much better harmonic profile of the input waveform, reduced dv/dt stress, possibility of fault tolerant operation, and so on. The use of higher number of semiconductor devices which are relatively more prone to faults plays a crucial role in determining the reliability of the system. In recent literature the performance analysis of the MLR in terms of cost, efficiency, reliability, and voltage stress has been majorly ignored. A five‐level rectifier topology with self‐voltage balancing capability has been implemented in this paper. The implemented topology has the capability to maintain the unity power factor (UPF) in all operating conditions. The in‐depth performance analysis in terms of reliability, efficiency and cost has been carried out to establish the suitability of the implemented topology for real‐time applications. In addition, the effect of various parameters on reliability has also been investigated. The MLR topology has been validated through experimentation. A qualitative and quantitative comparison of the proposed work with state‐of‐art has also been presented.