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Double-Gate Junctionless 1T DRAM With Physical Barriers for Retention Improvement

Md. Hasan Raza Ansari, Nupur Navlakha, Jae Yoon Lee, Seongjae Cho

2020IEEE Transactions on Electron Devices37 citationsDOI

Abstract

In this article, a double-gate (DG) junction-less (JL) transistor with physical barriers is proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this topology, the holes are stored in the region blocked by physical barriers constructed by oxides underneath the source and drain regions rather than a potential well formed by n+-p-n+ as in the conventional structures. The proposed topology achieves an elongated retention time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ret</sub> ) with larger physical barrier thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oxPB</sub> ) and wider barrier offset length (LBO) due to a reduction in band-to-band tunneling (BTBT) (during hold “0”) and recombination (during hold “1”). Maximum retention times of ~2.5 s and ~33 ms have been achieved for channel doping of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> at 27 °C and 85 °C, respectively, with gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) of 100 nm at small drain bias (VDS) of 1 V during write “1.” Results demonstrate a better gate length scalability and a retention time of ~4 ms at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> of 15 nm with thinner Si channel thickness under the gate (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Si</sub> ) and thicker T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oxPB</sub> . In addition, the effect of temperature on retention time has been analyzed. With optimized T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oxPB</sub> at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 100 nm, the retention time decreases due to thermal generation and recombination from ~2.5 s at 27 °C to ~3 ms at 125 °C.

Topics & Concepts

DramScalabilityTopology (electrical circuits)PhysicsQuantum tunnellingTransistorOptoelectronicsComputer scienceElectrical engineeringEngineeringQuantum mechanicsDatabaseVoltageSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignAdvanced Memory and Neural Computing
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