A 128-Channel AC-Coupled 1<sup>st</sup>-order Δ-Δ∑ IC for Neural Signal Acquisition
Xiaolin Yang, Marco Ballini, Chutham Sawigun, Wen-Yang Hsu, Jan-Willem Weijers, Jan Putzeys, Carolina Mora López
Abstract
In this paper, we present a miniature 128-channel neural recording IC (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs). An AC-coupled 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -order Δ-ΔΣ architecture is proposed to achieve rail-to-rail electrode DC offset rejection, low power and small area, while providing low noise and larger input range compared to other AC-coupled designs. This digitally-intensive architecture leverages the advantages of a highly-scaled technology node (22nm FD-SOI). The fabricated NRIC achieves a total area per channel of 0.005mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a total power per channel of 8.3μW, and an input-referred noise of 7.7±0.4μV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</inf> in the AP band and 11.9±1.1μV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</inf> in the LFP band. The chip has been fully validated in saline, demonstrating its capability to successfully record full-band neural signals.