A 28nm 4Mb Embedded RRAM IP with Record-High Endurance of 10<sup>7</sup> Cycles and 10 Years@125°C Retention through Reliability-Enhanced Design-Technology Co-Optimization
Junyang Zhang, Xiangchao Ma, Yue Xi, Yuyao Lu, Kun Wang, Hanyu Ren, Jianshi Tang, Liyang Pan, Lei Chen, Dong Wu, Bin Gao, He Qian, Huaqiang Wu
Abstract
The reliability issue has long been recognized as the primary impediment to embedded resistive random-access memory (RRAM) IP in advanced technology nodes. In this work, to address the multifaceted challenges brought by scaling, and simultaneously achieve exceptional retention and endurance performance, we implement a reliability-enhanced design-technology co-optimization (DTCO) methodology that encompasses multiple device and design innovations. It enables us to realize a highly reliable 4Mb embedded RRAM IP on a commercial 28nm Si CMOS platform, featuring 4 bits/cell multi-level-cell (MLC) capability, exceptional read disturb immunity of 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> counts, > 10 years@125°C retention and record-high endurance of 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cycles at 6Kb sub-macro and 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cycles at the chip level. All metrics are better than or on par with state-of-the-art RRAM technology reported so far. Further, the DTCO methodology developed in this work is applicable to more advanced technology nodes.