Static Performance and Reliability of 4H-SiC Diodes with P+ Regions Formed by Various Profiles and Temperatures
Stephen A. Mancini, Seung Yup Jang, Zeyu Chen, Dongyoung Kim, Justin Lynch, Yafei Liu, Balaji Raghothamachar, Minseok Kang, Anant Agarwal, Nadeemullah A. Mahadik, Robert E. Stahlbush, Michael Dudley, Woongje Sung
Abstract
Several designs of 1.2kV-rated 4H-SiC PiN diodes and Junction Barrier Schottky (JBS) diodes have been successfully fabricated with various P+ implantation conditions resulting in different junction profiles. P+ regions were implanted at both room temperature and elevated temperature (600˚C) to monitor the generation of Basal Plane Dislocations (BPDs) and study their impact on device long term reliability. It was found that, when the dose in the deeper portion of the junction (implemented by high energy implantations) is well suppressed, static and long-term reliability performances of room temperature implanted devices can be maintained similar to those of high temperature implanted devices.