Design of low power high-speed full, swing 11T CNTFET adder
Bhagyaveni Marchala Anjaneyulu, N.Siva Sankara Reddy
Abstract
As the semiconductor industry continues to decrease in size, it faces many issues, such as scalability, leakage, short-channel effects, and reliability. carbon nanotubes (CNT) has become a potential new technology that can address the shortcomings of CMOS without compromising both performance and reliability. The research presents the design, simulation, and comparison of an improved full-swing 11 Transistor (11T) adder based on CNT with a CMOS implementation in the 32 nm technological node. The CNT-based adder demonstrated superior performance compared to CMOS-based equivalents in terms of power consumption and delay, along with the power-delay product (PDP). The CNTFET adder demonstrates a minimum power consumption reduction of 73%, a minimum decrease in delay of 29%, and a minimum reduction in the power-delay product (PDP) of 81% when compared to the CMOS version of the adder with supply voltage ranging from 0.8 V to 1.2 V. The CNTFET adder demonstrates a minimum power consumption reduction of 64%, a minimum decrease in delay of 19%, and a minimum reduction in the power-delay product (PDP) of 71% when compared to the CMOS version of the adder with temperature ranging from -25°C to 75°C.