Trading Latency for Compute in the Network
Pietro Bressana, Noa Zilberman, Dejan Vučinić, Robert Soulé
Abstract
This paper proposes a new heterogeneous approach to programmable architecture that extends the capabilities of programmable switch ASICs with FPGAs. It identifies the key challenges in building a heterogeneous network architecture, and presents a concrete design and implementation based around a proof-of-concept data deduplication application. Our prototype demonstrates the use of a programmable network switch and FPGAs to accelerate storage fingerprinting, running at 10G and 100G at line rate. Our approach is modular, scalable and generalizes to a wide range of applications.
Topics & Concepts
Computer scienceField-programmable gate arrayScalabilityModular designComputer architectureData deduplicationKey (lock)Latency (audio)Embedded systemArchitectureLow latency (capital markets)Distributed computingComputer networkOperating systemTelecommunicationsArtVisual artsSoftware-Defined Networks and 5GInterconnection Networks and SystemsCaching and Content Delivery