Physics-based Computational Optimization in Dopingless Vertical Nanowire TFET using Triple Metal Gate Architecture
Anjana Bhardwaj, Amit Das, Swarnima Roy, Khushboo Khushboo, Abhishek Aman, Geetanjali Raj
Abstract
Abstract This paper proposes a triple metal gate electrostatically doped vertical nanowire tunnel field effect transistor (TMG-E-D-V-NW-TFET) by designing and analyzing its structure using the electrostatically doped (ED) V-NW-TFET structure using the triple metal gate (TMG) approach. The single metal gate E-D-V-NW-TFET (SMG-E-D-V-NW-TFET) and double metal gate E-D-V-NW-TFET (DMG-E-D-V-NW-TFET) architectures are contrasted with the proposed structure, TMG-E-D-V-NW-TFET. The proposed TMG-E-D-V-NW-TFET structure produced good results for the parameters such as on-current (ION), off-current (IOFF), and the current ratios (ION/IOFF) when three structures – SMG, DMG, and TMG – were compared. For the proposed structure, an analogue and RF analysis was done and compared with SMG and DMG, yielding better performance for characteristics like drain current against gate voltage (ID-VGS), transconductance (gm), and drain to gate capacitance (CGD), drain to source capacitance (CGS), total gate capacitance (CGG) and cut-off frequency (fT) etc. Next, the proposed device is compared with the structural outcomes. To show its applicability in nano-scale device architectures, a comprehensive comparison is made between all the three structures.