Assertion & Functional Coverage Driven Verification of AMBA Advance Peripheral Bus Protocol Using System Verilog
Prashant Dwivedi, Neha Mishra, Amit Singh-Rajput
Abstract
Design and Verification of the AMBA based Advanced Peripheral bus is presented in this paper. Verification environment is constructed using the System Verilog, it has features like Functional coverage, Assertion coverage, constrained Randomization and Code coverage.; Functional coverage makes sure that Hardware Descriptive Language (HDL) Code written performs all the functionality described in the Design specification; Code coverage shows total RTL codes is covered by the test cases. Assertions are used as additional checkers for making sure there are no protocol violation in the designed protocol. APB 4.0 protocol is completely designed and verified, there is no data loss in the designed system, AMBA's APB is used for low power low-cost interfacing of high speed and low speed Systems. This paper focuses on APB protocols verification and covers all the internal transactions of the APB protocol, complete cycle for designing of the verification environment is discussed in detail, the designed system can be successfully implemented in any Microcontroller system having very high and low speed peripherals. Designing is done by Verilog HDL using Mentor graphics tools Questa and Precision Pro is used for simulation of the Verification Environment respectively. 100 percentage Functional coverage with 1030 Bins & 97 percentage code coverage is achieved.