FPGA-Based Parallel Prefix Speculative Adder for Fast Computation Application
Garima Thakur, Harsh Sohal, Shruti Jain
Abstract
Approximate computing provides the tradeoff between the accuracy, the speed as well as power consumption. Approximate adders and other logical circuits can reduce hardware overhead. In this paper non-speculative and speculative parallel prefix adder is proposed and makes it more reliable to be used in applications where high speed circuits are required. If there is misprediction of result in speculative adder then error-correction is activated in the next clock cycle. Speculation is a process in which approximation is done. Approximate computing is widely used in the current scenario. The speculative adder reduces the critical path and provides the trade-off between reliability and performance. Proposed speculative parallel prefix adder results in 8.204ns delay which shows 36.87%, 2.35%, 26.32 % improvement in comparison to conventional NSA, proposed NSA, and conventional SA. Architecture is implemented for 16-bit operand length and used is an FPGA-based processing application.