6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier
Byoung-Joo Yoo, Dong‐Hyuk Lim, Hyonguk Pang, June-Hee Lee, Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young‐Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, WooChul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sanghune Park, Michael Choi, Jongshin Shin
Abstract
Needs for I/O bandwidth have rapidly increased with the explosive growth of internet traffic and data technologies. To accommodate the required high bandwidth, a DSP-based PAM-4 transceiver became the most robust solution with increased usage of channel capacity [1]–[4]. However, to be integrated with many transceivers in a chip, low-power designs are becoming critical factors for DSP-based transceivers. This paper presents an MM-CDR-based ADC timing skew control, which greatly reduces ADC complexity and power, and a low-power DSP using an approximate multiplier. Besides this, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{g}_{\mathrm{m}}$</tex> boosting of the TX driver and low-power TX DAC help reduce total power consumption.