The Optimal Solution of Fan-Out Embedded Bridge (FO-EB) Package Evaluation during the Process and Reliability Test
Vito Lin, David Lai, Yu-Po Wang
Abstract
High digital transmission was demanded for high performance computing (HPC) in recent years. In order to meet this target, high-bandwidth memories (HBM) are integrated with GPU or ASIC dies to form a heterogeneous integrated package (HIP).This HIP can be divided by three group: silicon dies, fan-out routing technology, organic interposer-selectively replaced by silicon bridge die to result in increased semiconductor assembly processes and reliability challenges, such as wafer warpage issue, chip module warpage, package warpage, compound crack risk.This paper will provide the optimal solution for the assembly processes and reliability challenges. In the beginning, glass and compound candidates would be studied for wafer warpage in pre-molding, u-pad, die bonding, underfill and 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> molding process. Regarding this subject, it would come out the glass and compound combinations which could be in criteria during the wafer warpage process. The compound candidates would be in parallel with chip module warpage and package warpage investigation to check the performance to meet the warpage target or not. After all warpage investigations, FO-EB would suffer compound crack issue after the reliability test. Hybrid adhesive material combination, heat sink adhesive pattern may be the solution for compound crack risk.In the validation, simulation shows good alignment with experimental results on stress and warpage prediction. According to that, F O-EB package could be qualified pass and mass production.