Seven-Level Packed U-Cell (PUC) Converter With Natural Balancing of Capacitor Voltages
Rajesh Vasu, Sumit K. Chattopadhyay, Chandan Chakraborty
Abstract
A seven-level packed U-cell inverter is presented in this article. The converter uses a single dc source and two floating capacitors, whose voltages are balanced in open loop, to produce multilevel output voltage. Peak magnitude of the output phase voltage is equal to the magnitude of dc source. Voltages across floating capacitors add intermediate voltage-levels by establishing an asymmetric ratio (with respect to the available dc voltage in the circuit). The average energy exchange (when the network is in steady state) of the capacitors with the rest of the inverter circuit will be zero. This helps the capacitors to maintain desired voltages and thus create intermediate levels of steady dc voltages. Performance of the converter is validated in simulation by MATLAB/Simulink and testing of the converter is done for resistive as well as inductive loads. Experimental verification of the converter is carried out on a laboratory prototype and the obtained results match well with the simulation.