A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics
Yize Wang, Guangyi Lu, Yuan Wang
Abstract
A new behavioral model of gate-grounded NMOS (ggNMOS) device is proposed for electrostatic discharge (ESD) simulation of snapback behavior. The concise snapback model is a solution for the lack of snapback characteristics of build-in SPICE models in high voltage conditions. Modeling analysis, verification of snapback behavior and transient response under ESD stress are shown in this work. The new snapback model is intuitive to be understood and useful for ESD designers who do not have extensive modeling experience and skills. All the parameters in the proposed model like triggering voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t1</sub> ), holding voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</sub> ) and on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) can be directly extracted by transmission line pulsing (TLP) test. Further, simulation of transient response to human body model (HBM) stress is performed and the predicted currents and voltages are verified by the relevant HBM test.