Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors
Jie Gu, Qingzhu Zhang, Zhenhua Wu, Yanna Luo, Lei Cao, Yuwei Cai, Jiaxin Yao, Zhaohao Zhang, Gaobo Xu, Huaxiang Yin, Jun Luo, Wenwu Wang
Abstract
A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ </tex-math></inline-formula> ) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.