Ferroelectric HfO<sub>2</sub> Memory Transistors With High-<i>κ</i> Interfacial Layer and Write Endurance Exceeding 10<sup>10</sup> Cycles
Ava J. Tan, Yu-Hung Liao, Li‐Chen Wang, Nirmaan Shanker, Jong‐Ho Bae, Chenming Hu, Sayeef Salahuddin
Abstract
We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cycles. The ferroelectric transistors (FeFETs) incorporate a high- κ interfacial layer (IL) of thermally grown silicon nitride (SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) and a thin 4.5 nm layer of Zr-doped FE-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) on a ~30 nm silicon on insulator (SOI) channel. The device shows a ~1V memory window (MW) in a DC sweep of just ± 2.5V, and can be programmed and erased with voltage pulses of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> G</sub> = ± 3V at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.