Power System Frequency and Phasor Estimation for a Low-Cost Synchrophasor Device Using the Nonlinear Least-Square Method
Atul Singh, S. K. Parida
Abstract
Wide area monitoring, protection, and control has now become an essential infrastructure to run an interconnected power system. To accomplish this by using synchrophasor technology, a wide range of phasor measurement unit (PMU) designs are available in the literature, but most of them are very costly because of the requirement of a high-speed processor to run complex algorithms. In this article, an algorithm for the synchrophasor and frequency estimation is proposed for processing platforms with low computational resources and is delineated extensively in respect of both accuracy and processing time. The proposed solution harnesses the main advantages of two well-known algorithms, viz. the zero-crossing detection and nonlinear least-squares method. Both algorithms are incorporated in a computationally efficient manner to reduce the processing time up to a lower extent while maintaining a good accuracy as per the standard IEEE testing conditions. The performance of the proposed algorithm has been evaluated through simulations as well as experimentally on the Raspberry Pi board. The consistency of the test results and minimum processing time provides clear evidence that the implemented design is suitable for PMU prototyping and is compliant with the mandatory IEEE standard C37.118.1-2011 and its amendment IEEE C37.118.1a-2014.