FPGA implementation of LDPC decoder for 5G NR with parallel layered architecture and adaptive normalization
Alexandr Katyushnyj, Aleksei Krylov, Andrey Rashich, Chao Zhang, Kewu Peng
Abstract
This paper presents the FPGA ASIC-like implementation of LDPC decoder for 5G NR BG2 and single lifting factor. The proposed implementation has two main features: architectural and algorithmic. The first is the parallel layered architecture with special offsets and inter-layer network which provides great scalability for variable lifting factors support. The second one is an adaptive normalization approach to increase decoder BER performance. The proposed implementation requires relatively small number resources of Xilinx Kintex Ultrascale FPGA and provides 1 information bit/s/cycle throughput for 10 iterations.
Topics & Concepts
Field-programmable gate arrayComputer scienceLow-density parity-check codeNormalization (sociology)ScalabilityParallel computingApplication-specific integrated circuitComputer architectureDecoding methodsArchitectureThroughputComputer engineeringAlgorithmComputer hardwareVisual artsDatabaseTelecommunicationsAnthropologyWirelessArtSociologyError Correcting Code TechniquesAdvanced Wireless Communication TechniquesTelecommunications and Broadcasting Technologies