A Survey of Graph Neural Networks for Electronic Design Automation

Daniela Sánchez Lopera, Lorenzo Servadei, Gamze Naz Kiprit, Souvik Hazra, Robert Wille, Wolfgang Ecker

202183 citationsDOI

Abstract

Driven by Moore’s law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource-demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate RTLs, and netlists. In this paper, we present a comprehensive review of the existing works linking the EDA flow for chip design and Graph Neural Networks.

Topics & Concepts

Electronic design automationComputer scienceDesign flowScalabilityData-flow analysisGraphIntegrated circuit designPhysical designAutomationPlacementArtificial neural networkTheoretical computer scienceDistributed computingComputer architectureEmbedded systemData flow diagramCircuit designMachine learningEngineeringMechanical engineeringDatabaseAdvanced Graph Neural NetworksAdvanced Memory and Neural ComputingMachine Learning in Materials Science