Fabrication and characterization of silicon-on-insulator wafers
Taeyeong Kim, Jungchul Lee
Abstract
Abstract Silicon-on-insulator (SOI) wafers offer significant advantages for both Integrated circuits (ICs) and microelectromechanical systems (MEMS) devices with their buried oxide layer improving electrical isolation and etch stop function. For past a few decades, various approaches have been investigated to make SOI wafers and they tend to exhibit strength and weakness. In this review, we aim to overview different manufacturing routes for SOI wafers with specific focus on advantages and inherent challenges. Then, we look into how SOI wafers are characterized for quality assessment and control. We also provide insights towards potential future directions of SOI technology to further accelerate ever-growing IC and MEMS industries.