Route Toward Commercially Manufacturable Vertical GaN Devices
Karen Geens, Matteo Borga, Md Arif Khan, Walter Gonçalez Filho, Anurag Vohra, Sourish Banerjee, K. J. Lee, Urmimala Chatterjee, Deepthi Cingu, Benoit Bakeroot, Stefaan Decoutere
Abstract
To make vertical GaN-based trench gate MOSFET devices commercially manufacturable, 200 mm engineered substrates with a poly-AlN core are a good substrate choice. The poly-AlN core, matched in thermal expansion to GaN, allows to grow high-quality thick GaN layers. Up to 11 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m-thick GaN stacks were grown crack-free, with excellent control over the wafer warp. Breakdown values of 900 V were reached for the vertical p/n-junction. Full device processing was completed in a CMOS-compatible pilot line without any wafer breakage, demonstrating the mechanical strength of these substrates. On module level, a new gate trench profile combining a smooth sidewall and round corners, is presented. While a smooth sidewall is important for the ON-state performance of the devices, the rounded corners are beneficial for the OFF-state operation. A semi-vertical test vehicle was used to demonstrate the ON-state of the fabricated power transistors. For devices with an effective gate width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{W}_{\text{G,\text{ef}\text{f}}}\text{)}$</tex-math> </inline-formula> of 180 mm and an active area of 1.4 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text{2}}$</tex-math> </inline-formula> , an ON-state resistance could be achieved of 8 m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega\cdot \text{cm}^{\text{2}}$</tex-math> </inline-formula> . By scaling the source contact length down, the device footprint could be decreased further. It is shown that for devices with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{W}_{\text{G,\text{ef}\text{f}}}$</tex-math> </inline-formula> of 60 mm this value could be further improved with best performing devices showing a 6.2 m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega\cdot\text{ cm}^{\text{2}}$</tex-math> </inline-formula> ON-state resistance.