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Wafer-scale integration of double gated WS<sub>2</sub>-transistors in 300mm Si CMOS fab

Inge Asselberghs, Quentin Smets, T. Schram, Benjamin Groven, Devin Verreck, Aryan Afzalian, Goutham Arutchelvan, Abhinav Gaur, Daire Cott, T. Maurice, Steven Brems, Koen Kennes, Alain Phommahaxay, Emmanuel Dupuy, D. Radisic, J-F de Marneffe, Arame Thiam, W. Li, K. Devriendt, Cedric Huyghebaert, Dennis Lin, Matty Caymax, P. Morin, Iuliana Radu

202055 citationsDOI

Abstract

Double gated WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistors with gate length down to 18 nm are fabricated in a 300mm Si CMOS fab. By using large statistical data sets and mapping uniformity on full 300mm wafer, we built an integration vehicle where impact of each process step can be understood and developed accordingly to enhance device performance. In-depth analysis of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability reveals multiple possible sources at different length scales, with the most prominent one being the channel material. The work presented here paves the way towards industrial adoption of 2D materials.

Topics & Concepts

CMOSTransistorWaferChannel (broadcasting)Scale (ratio)Process (computing)Computer scienceMaterials scienceElectrical engineeringOptoelectronicsEngineeringPhysicsVoltageOperating systemQuantum mechanicsAdvancements in Semiconductor Devices and Circuit DesignSemiconductor materials and devicesNanowire Synthesis and Applications
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