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A 21.8–41.6-GHz Low Jitter and High FoM<i>j</i> Fast-Locking Subsampling PLL With Dead Zone Automatic Controller

Wen Chen, Yiyang Shu, Jun Yin, Pui‐In Mak, Xiang Gao, Xun Luo

2024IEEE Transactions on Microwave Theory and Techniques10 citationsDOIOpen Access PDF

Abstract

In this article, a wideband millimeter-wave (mm-wave) fast-locking subsampling phase-locked loop (FL-SSPLL) with low jitter and high jitter-power figure of merit (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\bm{j}}$</tex-math> </inline-formula> ) is proposed. A quadrature subsampling phase detector (QSSPD)-based dead zone automatic controller (DZAC) is introduced for fast locking. Such DZAC eliminates the long locking time caused by the dead zone of frequency-locked loop (FLL) while maintaining low in-band phase noise of subsampling loop (SSL). The mm-wave quad-mode oscillator is integrated in the FL-SSPLL to achieve a wide frequency range. The proposed FL-SSPLL is fabricated in a 40-nm CMOS technology and occupies a core area of 0.18 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> . Measurements exhibit a wide output frequency range of 62.5% from 21.8 to 41.6 GHz with a 100-MHz reference. The FL-SSPLL achieves a 62.7–79.1-fs root-mean-square (rms) jitter across the whole frequency range. The total power consumption is 18.3–23.6 mW, leading to FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\bm{j}}$</tex-math> </inline-formula> from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 248.3 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 251.4 dB. Meanwhile, the FL-SSPLL features a robust lock acquisition and achieves less than 1.5- <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <inline-formula> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> </b> s locking time.

Topics & Concepts

JitterPhase-locked loopDead zoneElectronic engineeringComputer scienceController (irrigation)Electrical engineeringPhysicsEngineeringGeologyBiologyOceanographyAgronomyAdvancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignPhotonic and Optical Devices
A 21.8–41.6-GHz Low Jitter and High FoM<i>j</i> Fast-Locking Subsampling PLL With Dead Zone Automatic Controller | Litcius